Fraunhofer Institute for Applied and Integrated Security Fraunhofer AISEC: Security features for trusted electronics
European Chiplet Innovation: APECS Pilot Line starts Operation in the Framework of the EU Chips Act
The pilot line for “Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems” (APECS) marks a major leap forward in strengthening Europe’s semi-conductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. APECS will make a significant contribution to the European Union´s goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. In APECS the Fraunhofer Institute for Applied and Integrated Security AISEC develops security features for trusted electronics in the heterointegration of chiplets.
Europe is home to a vibrant ecosystem of (hidden) champions, from traditional enterprises in vertical markets, to SMEs and start-ups the competitive advantages of which lie in superior semiconductor-based solutions. Nevertheless, many of these companies are currently confronted with limited access to advanced semiconductor technologies, while at the same time these technologies are increasingly becoming the most important factor for innovation and market growth.
The European Commission is investing significant resources under the EU Chips Act to strengthen semiconductor technologies and applications in the European Union. This aims to enhance Europe’s technological resilience, secure supply and value chains, and drive innovation in emerging fields such as energy efficient AI, manufacturing, mobility, information and communications, neuromorphic and quantum computing as well as trusted and sustainable electronics.
The APECS pilot line focuses on bridging application-oriented research with innovative developments in heterogeneous integration*, in particular emerging chiplet** technologies. By pushing beyond conventional system-in-package (SiP) methods, APECS will deliver robust and trusted heterogeneous systems, significantly boosting the innovation capacity of the European semiconductor industry.
Innovation where European industries need it the most
The APECS pilot line will play a key role in supporting European microelectronics by developing new system integration technologies and unlocking new functionalities within the system-technology co-optimization (STCO) approach. This will enable European companies to develop advanced products, even in low quantities, at competitive costs. By providing a wide range of technologies on a single platform, APECS is positioned to become Europe’s leading hub for the development of advanced packaging and heterogeneous integration.
APECS will be a key driver of collaboration among European RTOs, industry and academia, fostering a lively innovation ecosystem. Customers will benefit from a single point of contact to the APECS pilot line. APECS will cover end-to-end design and pilot production capabilities and accelerate progress from cutting-edge research to practical, scalable manufacturing solutions.
Security for the Heterogeneous Integration of Chiplets
In establishing the pilot line, security experts contribute to the development of security chiplets and conduct security analyses of chiplet-based and heterogeneously integrated systems.
To ensure trusted systems, Fraunhofer AISEC, in collaboration with partner institutes, will develop hardware trust anchors for chiplets. These trust anchors within the chiplet form the foundation for authenticating the chiplet system and its components internally and to third parties. Only then can the chiplet combine with others to create a secure and trustworthy overall system. Chiplet security is rooted in security primitives such as key storage, random number generators, or tamper detection circuits. Fraunhofer AISEC analyzes chiplet technologies for new physical primitives and designs proofs of concept for IP blocks that utilize both established and novel hardware primitives, translating them into chiplet-specific functions.
For APECS, Fraunhofer AISEC researches, designs, and implements integrated hardware-software security solutions tailored to RISC-V-based chiplet architectures. In this context, security mechanisms can benefit from the chiplet-specific environment, such as fast communication between various hardware modules and shared resources.
Another goal is to research, design, and implement security analysis techniques. Physical security analyses involve several interconnected steps, from preparation and localization of critical components to analyzing actual security functionality. All steps are conducted together in a secure environment. Fraunhofer AISEC, together with its partners, provides an optimized security analysis process with clear interfaces and services for the pilot line.
About funding: € 730 million over 4.5 years
Fließtext APECS is co-funded by the Chips Joint Undertaking and nation-l funding authorities of Austria, Belgium, Finland, France, Germany, Greece, Portugal, Spain, through the “Chips for Europe” initiative. The overall funding for APECS amounts to € 730 million over 4.5 years.
About partners: Boosting Innovation through strong multilevel Collaboration
The APECS consortium brings together the technological competences, infrastructure, and know-how of ten partners from eight European countries: Germany (Fraunhofer-Gesellschaft as coordinator, FBH, IHP), Austria (TU Graz), Finland (VTT), Belgium (imec), France (CEA-Leti), Greece (FORTH), Spain (IMB-CNM, CSIC) and Portugal (INL). APECS is coordinated by the Fraunhofer-Gesellschaft and implemented by the Research Fab Microelectronics Germany (FMD).
*About Heterogeneous Integration
Semiconductor research and development is at the core of current technological (r)evolutions, ranging from artificial intelligence and high-performance computing, modern defense systems to robotics, power electronics, wireless communication, e-health care, quantum technologies, and more. Such future electronic systems will require more and more functions that cannot be provided by a single chip, even if advanced system-on-chip (SoC) concepts are used. Heterogeneous integration will go beyond current system-in-package (SiP) approaches. This concept of true heterogeneous integration is extremely important for next-generation devices based on future CMOS nodes, SiGe, SiC, III/Vs such as GaAs or GaN and all different types of microelectromechanical systems (MEMS).
**About Chiplets
For conventional approaches, the amount of data to be stored is too big, the data transfer rates are too low, the available computational power is limiting, and the energy consumption, as well as the heat production of general-purpose computer processing units (CPUs) are too high. In addition, the increasingly higher costs for further node miniaturization in the IC manufacturing process will also promote the interconnection of so called chiplets. This means that intellectual property (IP) blocks made in different technology nodes will be combined on an active interposer to reduce cost by increasing the production yield (smaller chips) and reuse across applications. This will also touch upon environmental properties of electronics in terms of resource efficiency, critical raw materials, modularity and reusability of design blocks.