Hardware Security

Security for integrated circuits

Hardware security focuses on attacks on and protection measures in integrated circuits, microchips, as well as modules of several microchips on circuit boards. The main tasks are divided into the defense against attackers with physical access to their targets and the provision of a basic hardware security layer on which further protective mechanisms, e.g., for the protection of operating systems, can be built.

The focus of the department Hardware Security is on security evaluation in the lab, on securing and integrating microcontrollers and secure elements, tampering protection, and on the reliable use of system-on-chips and FPGAs. In this context, research is conducted and published in areas of side-channel analysis of cryptographic implementations, fault attacks, hardware penetration testing, physical-unclonable functions (PUF), and the use of machine learning. The results extend the state of the art in evaluation and protection measures. This distinctive spectrum of expertise and the many years of experience, as well as the corresponding equipment landscape with tooling in the laboratory, allow complex systems to be examined for vulnerabilities and individual security solutions to be designed.

Labs

 

Hardware Security Lab

Our Hardware Security Lab offers a broad spectrum of hardware security analyses: from offensive security analysis of embedded systems to highly specialized attacks on security implementations.

 

Offerings

Working closely with our customers and partners, our goal is to systematically improve the ability to assess the security of systems and products in order to evaluate system reliability, design systems to be secure, and sustainably maintain security throughout their lifecycle.

Evaluate Security

  • Security or threat analyses of embedded systems - after a vulnerability has become known or beforehand
  • Evaluate security against requirements from norms and standards, for example in the IoT and medical areas
  • Concrete hardware security evaluations of products, chips, and systems in the lab
  • Evaluation of IoT products regarding hardware, firmware and (radio) communication security
  • Side-channel analyses and fault attacks on cryptographic implementations
  • Development of measuring stations and tooling for side-channel analysis and fault attacks according to customer requirement

 

Design Security

  • Customized security concepts for embedded systems and IoT products based on a trade-off between costs and security.
  • Security solutions based on informed selection and correct implementation of protection mechanisms of modern microcontrollers or system-on-chips as well as dedicated security chips
  • Ready-to-use security functions and cryptographic algorithms in firmware on microcontrollers and in hardware on FPGAs for IoT devices to implement, for example, encryption and secure updates

 

Maintain Security

  • Development of security roadmaps for products, especially with increasing regulatory requirements, e.g., in medical devices and IoT devices in general
  • Forward-looking security assessments and forecasts of challenges in the coming year

Expertise

Attacks

Side-channel attacks

Side-channel attacks are fundamentally different from conventional attacks on cryptographic algorithms. In the latter case, attackers attempt to solve a complex mathematical problem or search the entire key space to break cryptographic systems.  In contrast, side-channel attacks use information such as runtime, power consumption, or electromagnetic emission. Attackers can use this information to obtain secret data stored on the device. We evaluate the side-channel security of cryptographic implementations in our hardware lab using state-of-the-art high-precision measurement equipment and software. The knowledge generated there is used to design and implement countermeasures which are customized for a specific target platform.

Fault attacks

Fault attacks attempt to disrupt systems in a specific way. This can be accomplished by increasing or decreasing the supply voltage, by changing the frequency or the ambient temperature, or by deliberately disturbing the system using lasers or electromagnetic pulses. Combined with knowledge of the operating principle of a cryptographic algorithm, the intentionally induced errors can be used to gather information about the secret key processed internally. Likewise, it can be utilized to bypass memory protection measures or to activate debug interfaces. Laser-assisted error injection makes it possible to induce errors with very high accuracy (in terms of time and location). This gives the attacker more control and allows a wider range of attacks. Our hardware lab has two different laser stations to perform fault attacks and evaluate device security and countermeasures.

Machine Learning

Modern statistical methods, which are often summarized under the term machine learning, serve to improve the evaluation of complex data. Machine learning offers the necessary flexibility to make complex statistical correlations visible. In the Hardware Security department, various algorithms are used to evaluate measurement data from side-channel measurements and for anomaly detection in sensor networks. Machine learning not only helps to better understand sensor data on resource-constrained platforms or side-channel measurements with terabytes of data, but also opens up the application to a variety of new kinds of problems.

 

System Design

Internet-of-Things

Systems in the Internet-of-Things (IoT) typically have a long operating time, limited processing resources and a reduced battery life. In the process, they may also incur only low costs in production and operation. Due to these constraints, many of the established security technologies cannot be directly transferred to the IoT domain. One research focus of the department Hardware Security therefore lies on innovative hardware and software design patterns that aim to increase the resilience of IoT devices with limited resources against cyber attacks. These include, for example, memory protection mechanisms, system attestation and identities, and measures against denial-of-service attacks.

Medical Devices

Connected medical devices and so-called wearables, such as continuous glucose monitors or implanted pacemakers, are exposed to high risks of attack due to their increasing distribution and functionality. Based on our analysis and solution expertise from hardware to networks security, we help manufacturers to design secure devices that also meet the requirements of the new Medical Device Regulation (MDR).

Sensor Networks

Wireless sensor networks are the sensory organs of the Internet-of-Things. Often, the collected data is critical and must be protected against eavesdropping or manipulation. The management of the cryptographic keys required for this purpose is challenging due to the large number of sensor nodes and their limited computing power. We are therefore continuously expanding our expertise in the field of key management solutions that combine security and user-friendliness and enable any user to easily operate secure wireless sensor networks.

System-on-Chips

Systems-on-chips (SoCs) combine a multitude of functions in a single chip. They are the foundation of countless embedded systems and must therefore be protected carefully. The many functions of an SoC provide a large surface for attack, which makes securing them a major challenge. Debug interfaces and external memory modules must be secured, cryptographic keys must be stored in a secure manner, and software must be executed securely. Secure boot and update, firmware encryption, key storage, protection of intellectual property and secure execution environments are just some of the topics that have been the focus of the Hardware Security department for years.

Tamper Protection

Embedded systems are exposed to physical tampering to manipulate the system or derive critical secrets, especially in the domain of high-assurance communication. Detecting and reacting to tampering requires the interaction of sensor technologies, electronics and embedded security. We are collaborating with technology partners to design new tamper protection methods, in particular based on Physical Unclonable Function (PUFs) to assess the physical integrity of a device based on the validity of a physical hardware fingerprint.

 

Hardware Design

FPGAs und PUFs

The use of programmable hardware, so-called Field Programmable Gate Arrays (FPGAs), in embedded systems and as part of high-performance systems-on-chip is growing rapidly. In this context, purchased third-party designs can compromise the security of the overall system from the inside. Our security reviews identify specific points of attack and help to secure systems at an early stage. Another research area deals with the use of FPGAs as a basis for Physical Unclonable Functions (PUFs). PUFs are circuits that use manufacturing variations to create a unique bit string. This can then be used to bind cryptographic keys or uniquely identify a chip. PUFs can be used in FPGA applications to provide the user with a secure key store without relying on security features provided by the manufacturer. These are often less trustworthy and more vulnerable to attack. Here, an array of over 200 FPGAs allows us to analyze the statistical properties of improved and novel implementations of PUF circuits on FPGAs.

Trusted Electronics

Securing electronics supply chains and the topic of secure open-source hardware, especially RISC-V based system-on-chips, have become more important in recent years. We use our competencies in electronics security here and research RISC-V based designs and hardened crypto accelerators, as well as improved test methods for evaluating trustworthiness.

Selected Projects

Post-CMOS Drucksensor-Chiplets mit Wafer-level Gehäusen vor ihrer Separierung.
Post-CMOS pressure sensor chiplets with wafer level packaging before dicing.

European Chiplet Innovation: APECS Pilot Line in the Framework of the EU Chips Act

 

The pilot line for “Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems” (APECS) marks a major leap forward in strengthening Europe’s semi-conductor manufacturing capabilities and chiplet innovation as part of the EU Chips Act. APECS will make a significant contribution to the European Union´s goals of increasing technological resilience, strengthening cross-border collaboration and enhancing its global competitiveness in semiconductor technologies. 

In APECS the Fraunhofer Institute for Applied and Integrated Security AISEC develops security features for trusted electronics in the heterointegration of chiplets.

-> Press release

© AdobeStock/ Raimundas

Bavarian Chip Design Center


In view of global dependencies on microelectronic components and geopolitical instabilities, the semiconductor and chip production in Europe must be promoted more intensively. With the »Bavarian Chip Design Center« (BCDC), the German state of Bavaria is a making a significant contribution to achieving this goal.

In the BCDC, the Fraunhofer Institute for Applied and Integrated Security AISEC, the Fraunhofer Institute for Microsystems and Solid State Technologies EMFT and the Fraunhofer Institute for Integrated Circuits IIS are pooling their expertise in order to expand their IC design competence, establish a chip design ecosystem and provide accessible and at the same time low-risk approaches to chip design for small and medium-sized enterprises in particular.

Fraunhofer AISEC primarily contributes its know-how in the design, development and testing of secure and reliable systems. To this end, researchers are developing new security technologies and analytical methods for trusted electronics supply chains as well as security chips tailored to specific use cases. New operating system components closely interlocked with the hardware allow for secure software environments that are based on isolation mechanisms such as Trusted Execution Environments and Confidential Computing. Additionally, verified boot processes, secure firmware updates and architecture-based HW/SW countermeasures for protection against commonly exploited software vulnerabilities ensure continuous security in the system.

-> More information

Hardware Security Lab
Trusted electronics focus on secure designs, supply chains and analysis techniques.

Study on Trusted Electronics

Microchips are key parts of our daily lives. However, today’s hardware supply chains extend across the entire globe. Their complexity harbors cybersecurity risks such as unintended weaknesses, deliberately introduced backdoors and counterfeit components. To tackle these challenges, trusted electronics focuses on secure designs, supply chain security and analysis techniques. Developing secure and reliable electronics is crucial for Europe's technological sovereignty and trustworthy IT systems.

In the "Study on Trusted Electronics: An overview over requirements, technologies and initiatives towards more trusted electronics", Fraunhofer AISEC examines for the European Commission why trusted electronics are not yet widely used and what drives manufacturers to increase the trustworthiness of their devices. IT security researchers Dr. Matthias Hiller and Johanna Baehr explore relevant approaches to secure design, supply chain security and security analysis that increase the cybersecurity of embedded devices while meeting manufacturers' requirements. The study dives into examples for major initiatives on trusted electronics as well as standardization efforts and provides an overview of roadmaps and studies in the field.

Establishing dedicated funding programs and initiatives such as the European Chips Act, bridging the gap between research and real-world implementation and involving companies in large-scale deployment are key to boost the European design and manufacturing ecosystem and to pave the way for a secure and resilient digital Europe.

-> Read study

Velektronik

The goal of the research project "Velektronik" is to establish a networking platform for trusted electronics for Germany and thus create an interface between researchers and companies.

Under the overall coordination of Fraunhofer AISEC, various cooperation partners from the Fraunhofer-Gesellschaft and Leibniz Association will work together with the edacentrum in the Forschungsfabrik Mikroelektronik Deutschland (FMD) during the next three years to develop solution concepts for trusted electronics in all areas of electronics development and manufacturing.

Within the framework of the funding guideline for "Vertrauenswürdige Elektronik (ZEUS)" of the Federal Ministry of Education and Research (BMBF), overarching issues in the three main areas design, manufacturing and analysis of the microelectronics value chain will be addressed.

https://www.velektronik.de/en

Selected Initiatives and Collaborations

 

Fraunhofer CCIT

IoT communiation

In the Fraunhofer CCIT, we develop key technologies for the Internet of Things (IoT) to obtain reliable and secure sensor data. We combine and enhance solutions for networking, localization and information security.

 

High Performance Center

Secure Intelligent Systems

The High Performance Center »Secure Intelligent Systems« is an initiative of the Fraunhofer Institutes AISEC, EMFT, IBP, IGCV, IKS and IVV from Munich metropolitan region with the Technical University of Munich, the Universität der Bundeswehr München and the Munich University of Applied Sciences.

Publications

2024

  • Ivan Gavrilan, Felix Oberhansl, Alexander Wagner, Emanuele Strieder, Andreas Zankl: »Impeccable Keccak: Towards Fault Resilient SPHINCS+ Implementations«. In: IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2024.2 (2024), pp. 154–189. DOI: 10.46586/tches.v2024.i2.154-189.
  • Marc Schink, Alexander Wagner, Felix Oberhansl, Stefan Köckeis, Emanuele Strieder, Sven Freud, Dominik Klein: »Unlock the Door to my Secrets, but don’t Forget to Glitch: A Comprehensive Analysis of Flash Erase Suppression Attacks«. In: IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2024.2 (2024), pp. 88–129. DOI: 10.46586/tches.v2024.i2.88-129.
  • Johannes Geier, Lukas Auer, Daniel Mueller-Gritschneder, Uzair Sharif, Ulf Schlichtmann: »CompaSeC: A Compiler-Assisted Security Countermeasure to Address Instruction Skip Fault Attacks on RISC-V«. In: Proceedings of the 28th Asia and South Pacific Design Automation Conference (ASPDAC ’24), Association for Computing Machinery, New York, NY, USA, 2024, pp. 676–682. DOI: 10.1145/3566097.3567925.